View AS7C31026B-20BI_6622672.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

february 2004 copyright ? alliance semiconductor. all rights reserved. ? as7c31026b 3.3 v 64k x 16 cmos sram 2/27/04, v 1.2 alliance semiconductor p. 1 of 11 features ? industrial and commercial versions ? organization: 65,536 words 16 bits ? center power and ground pins for low noise ? high speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time ? low power consumption: active - 288 mw / max @ 10 ns ? low power consumption: standby - 18 mw / max cmos i/o ? 6 t 0.18 u cmos technology ? easy memory expansion with ce , oe inputs ? ttl-compatible, three-state i/o ? jedec standard packaging - 44-pin 400 mil soj - 44-pin tsop 2-400 - 48-ball 6 8 mm mbga ? esd protection 2000 volts ? latch-up current 200 ma logic block diagram 64 k 16 array oe ce we column decoder row decoder a0 a1 a2 a3 a4 a5 a7 v cc gnd a8 a9 a10 a11 a12 a13 a14 a15 control circuit i/o0?i/o7 i/o8?i/o15 ub lb i/o buffer a6 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o13 i/o12 gnd v cc i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 nc a0 ce i/o0 i/o1 i/o2 i/o3 v cc gnd i/o4 i/o5 i/o6 i/o7 we a15 a14 a13 44-pin soj (400 mil), tsop 2 21 22 a12 nc ub lb i/o15 i/o14 2 a3 3 a2 4 a1 1 a4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a6 a7 oe a5 as7c31026b selection guide -10 -12 -15 -20 unit maximum address access time 10 12 15 20 ns maximum output enab le access time 5678ns maximum operating current 80 75 70 65 ma maximum cmos standby current 5555ma 00000 48 - bga ball-grid-array package 1 2 345 6 alb oe a 0 a 1 a 2 nc bi/o8 ub a3 a4 ce i/o0 ci/o9 i/o10 a5 a6 i/o1 i/o2 dv ss i/o11 nc a7 i/o3 v dd ev dd i/o12 nc nc i/o4 v ss fi/o14 i/o13 a14 a15 i/o5 i/o6 g i/o15 nc a12 a13 we i/o7 hnc a8a9a10a11nc pin and ball arrangement
? as7c31026b 2/27/04, v 1.2 alliance semiconductor p. 2 of 11 functional description the as7c31026b is a high-performance cmos 1, 048,576-bit static random access memory (sram) devi ce organized as 65,536 words 16 bits. it is designed for memory a pplications where fast data access, low power, and si mple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with out put enable access times (t oe ) of 5, 6, 7, 8 ns are ideal for high-performance applications. when ce is high, the device enters standby mode. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o0 through i/o15 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ) with write enable (we ) high. the chips drive i/o pins with the data word referenced by the input a ddress. when either chip enable or output en able is inactive or write enable is act ive, output drivers stay in hi gh-impedance mode. the device provides multiple center power and ground pins, and separate byte enable cont rols, allowing individual bytes to be w ritten and read. lb controls the lower bits, i/o0 through i/o7, and ub controls the higher bits , i/o8 through i/o15. all chip inputs and outputs are ttl-compatib le, and operation is from a single 3.3 v su pply. the device is packaged in common i ndustry standard packages. chip scale bga packaging, easy to use in manufacturing, provides the smallest possible footprint. this 48-ba ll jedec- registered package has a ball pitch of 0.75 mm and external dimensi ons of 8 mm 6 mm. note: stresses greater than those listed under absolute maximum ratings may cause perman ent damage to the device. this is a str ess rating only and func- tional operation of the device at these or any other conditions ou tside those indicated in the oper ational sections of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. key: h = high, l = low, x = don?t care. absolute maximum ratings parameter symbol min max unit voltage on v cc relative to gnd v t1 ?0.50 +5.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc +0.50 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c ambient temperature with vcc applied t bias ?55 +125 c dc current into outputs (low) i out ?20ma truth table ce we oe lb ub i/o0?i/o7 i/o8?i/o15 mode h x x x x high z high z standby (i sb ), i sbi ) lhllhd out high z read i/o0?i/o7 (i cc ) l h l h l high z d out read i/o8?i/o15 (i cc) lhllld out d out read i/o0?i/o15 (i cc ) llxll d in d in write i/o0?i/o15 (i cc ) llxlh d in high z write i/o0?i/o7 (i cc ) l l x h l high z d in write i/o8?i/o15 (i cc ) l l h x h x x h x h high z high z output disable (i cc )
? as7c31026b 2/27/04, v 1.2 alliance semiconductor p. 3 of 11 v il = -1.0v for pulse width less than 5ns v ih = v cc + 1.5v for pulse width less than 5ns recommended operating conditions parameter symbol min nominal max unit supply voltage v cc 3.0 3.3 3.6 v input voltage v ih 2.0 ? v cc + 0.5 v v il ?0.5 ? 0.8 v ambient operatin g temperature commercial t a 0? 70 o c industrial t a ?40 ? 85 o c dc operating characteristic s (over the operating range) 1 parameter sym test conditions -10 -12 -15 -20 unit min max min max min max min max input leakage current | i li | v cc = max v in = gnd to v cc ?1?1?1?1a output leakage current | i lo | v cc = max ce = v ih , v out = gnd to v cc ?1?1?1?1a operating power supply current i cc v cc = max, ce v il , outputs open, f = f max = 1/t rc ?80?75 ? 70 ? 65ma standby power supply current i sb v cc = max, ce v il , outputs open, f = f max = 1/t rc ?30?25?20?20 ma i sb1 v cc = max, ce v cc ?0.2 v, v in gnd + 0.2 v or v in v cc ?0.2 v, f = 0 ?5?5?5?5 ma output voltage v ol i ol = 8 ma, v cc = min ? 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? 2.4 ? v capacitance (f = 1mhz, t a = 25 c, v cc = nominal) 2 parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe , lb , ub v in = 0 v 5 pf i/o capacitance c i/o i/o v in = v out = 0 v 7 pf
? as7c31026b 2/27/04, v 1.2 alliance semiconductor p. 4 of 11 key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read cycle (over the operating range) 3,9 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max read cycle time t rc 10?12?15?20?ns address access time t aa ?10?12?15?20ns3 chip enable (ce ) access time t ace ?10?12?15?20ns3 output enable (oe ) access time t oe ?5?6?7?8ns output hold from address change t oh 3?3?3?3?ns5 ce low to output in low z t clz 3?3?3?3?ns4, 5 ce high to output in high z t chz ?3?3?4?5ns4, 5 oe low to output in low z t olz 0?0?0?0?ns4, 5 byte select access time t ba ?5?6?7?8ns byte select low to low z t blz 0?0?0?0?ns4, 5 byte select high to high z t bhz ?5?6?6?8ns4, 5 oe high to output in high z t ohz ?5?6?7?8ns4, 5 power up time t pu 0?0?0?0?ns4, 5 power down time t pd ? 10 ? 12 ? 15 20 ns 4, 5 undefined output/don?t care falling input rising input t oh t aa t rc t oh data out address data valid previous data valid
? as7c31026b 2/27/04, v 1.2 alliance semiconductor p. 5 of 11 read waveform 2 (oe , ce , ub , lb controlled) 3,6,8,9 write cycle (over the operating range) 11 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max write cycle time t wc 10 ? 12 ? 15 ? 20 ? ns chip enable (ce ) to write end t cw 8?9?10?12? ns address setup to write end t aw 8?9?10?12? ns address setup time t as 0?0?0?0? ns write pulse width t wp 7 ? 8 ? 9 ? 12 ? ns write recovery time t wr 0?0?0?0? ns address hold from end of write t ah 0?0?0?0? ns data valid to write end t dw 5 ? 6 ? 8 ? 10 ? ns data hold time t dh 0?0?0?0? ns 5 write enable to output in high z t wz ? 5 ? 6 ? 7 ? 8 ns 4, 5 output active fr om write end t ow 1 ? 1 ? 1 ? 2 ? ns 4, 5 byte select low to end of write t bw 7?8?9?9? ns data valid t rc t aa t blz t ba t oe t olz t oh t ohz t hz t bhz t ace t lz address oe ce lb , ub data in
as7c31026b ? 2/27/04, v 1.2 alliance semiconductor p. 6 of 11 write waveform 1 (we controlled) 10,11 write waveform 2 (ce controlled) 10,11 address ce lb , ub we data in data out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t wr data undefined high z data valid t ah address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t ow t wz t wr data out data undefined high z high z t as t aw data valid t clz t ah
? as7c31026b 2/27/04, v 1.2 alliance semiconductor p. 7 of 11 ac test conditions notes 1 during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a and b. 4 these parameters are specified with c l = 5 pf, as in figures b. transition is me asured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address is valid prior to or coincident with ce transition low. 9 all read cycle timings are referen ced from the last valid address to the first transitioning address. 10 n/a 11 all write cycle timings are referenced from the la st valid address to the first transitioning address. 12 not applicable. 13 c = 30 pf, except all high z and low z parameters where c = 5 pf. 255 ? c 13 320 ? gnd +3.3 v figure b: 3.3 v output load 168 ? thevenin equivalent: d out +1.728 v (5 v and 3.3 v ) 10% 90% 10% 90% gnd +3.0 v figure a: input pulse 2 ns d out ? output load: see figure b. ? input pulse level: gnd to 3.0 v. see figure a. ? input rise and fall times: 2 ns. see figure a. ? input and output timing reference levels: 1.5
as7c31026b ? 2/27/04, v 1.2 alliance semiconductor p. 8 of 11 package dimensions 44-pin tsop 2 min (mm) max (mm) a 1.2 a1 0.05 0.15 a2 0.95 1.05 b 0.30 0.45 c 0.120 0.21 d 18.31 18.52 e 10.06 10.26 he 11.68 11.94 e 0.80 (typical) l 0.40 0.60 d he 1234567891011121314 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l a1 a2 e 44-pin tsop 2 0?5 21 24 22 23 e a b seating plane 44-pin soj 44-pin soj 400 mil min (in) max (in) a 0.128 0.148 a 1 0.025 ? a 2 0.105 0.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.120 1.130 e 0.370 nom e 1 0.395 0.405 e 2 0.435 0.445 e 0.050 nom e pin 1 a 1 b b a a 2 e 2 e 1 d c e
? as7c31026b 2/27/04, v 1.2 alliance semiconductor p. 9 of 11 notes 1 bump counts: 48 (8 row x 6 column). 2 pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3 units: millimeters. 4 all tolerance are 0.050 unless otherwise specified. 5 typ: typical. 6 y is coplanarity: 0.10 (max). minimum typical maximum a ?0.75? b 5.90 6.00 6.10 b1 ?3.75? c 7.90 8.00 8.10 c1 ?5.25? d 0.25 0.30 0.40 e ? ? 1.20 e2 0.17 0.22 0.27 y ? ? 0.10 48-ball bga bottom view 6 543 2 1 ball a1 c1 a b c d f g h j a b1 side view top view ball #a1 index c sram die elastomer b detail view a y die e2 e die d e2 e *pin 1 indicator will show as engraved circle and/or inc. trademark *
as7c31026b ? 2/27/04, v 1.2 alliance semiconductor p. 10 of 11 note: add suffix ?n? to the above part number for lead free parts (ex. as7c31026b-10jcn) ordering codes package\access time volt/temp 10 ns 12 ns 15 ns 20 ns plastic soj, 400 mil 3.3 v commercial as7c31026b-10jc as7c31026b-12jc as7c31026b-15jc as7c31026b-20jc 3.3 v industrial as7c31026b-10ji as7c31026b-12ji as7c31026b-15ji as7c31026b-20ji tsop 2, 10.2 x 18.4 mm 3.3 v commercial as7c31026b-10tc as7c31026b-12tc as7c31026b-15tc as7c31026b-20tc 3.3 v industrial as7c31026b-10ti as7c31026b-12ti as7c31026b-15ti as7c31026b-20ti bga, 6 x 8 mm 3.3 v commercial as7c31026b-10bc as7c31026b-12bc as7c31026b-15bc as7c31026b-20bc 3.3 v industrial as7c31026b-10bi as7c31026b-12bi as7c31026b-15bi AS7C31026B-20BI part numbering system as7c x 1026b ?xx x x x sram prefix voltage: 3 = 3.3 v cmos device number access time package: j = soj 400 mil t = tsop 2, 10.2 x 18.4 mm b = bga, 6 x 8 mm temperature range: c = commercial: 0 c to 70 c i = industrial: -40 c to 85 c n=lead free part
alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? allia nce semiconductor all rights reserved part number: as7c31026b document version: v 1.2 ? copyright 2003 alliance semicond uctor corporation. all rights reserved. our three-poi nt logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all othe r brand and product names may be the trademarks of their respective comp anies. alliance reserve s the right to make changes to this document and it s products at any time without notice. alliance a ssumes no responsibility for any errors that ma y appear in this document. the data contained herein represents allianc e's best data and/or estimates at the tim e of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the pr oduct described herein is un der development, significant changes to these specificat ions are possible. the information in this product data sheet is intended to be general descriptive informa tion for potential cust omers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does no t assume any responsibility or liability ar ising out of the application or use of any product described herein, an d disclaims any express or im plied warranties related to th e sale and/or use of allia nce products including liability or warranties related to fitness fo r a particular purpose, merchantability, or infringement of an y intellectual prope rty rights, except as express agreed to in alliance's terms and conditions of sale (which ar e available from alliance). all sa les of alliance products are ma de exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent r ights, copyrights; mask works rights, trademarks, or any other inte llectual property rights of alliance or thir d parties. alliance does not authorize i ts products for use as critical components in life-supporting syst ems where a malfunction or failure may reasonab ly be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems imp lies that the manufacturer assume s all risk of such use and a grees to indemnify alliance against all claims arising from such use. ? ? as7c31026b

▲Up To Search▲

Price & Availability of AS7C31026B-20BI

	To Download AS7C31026B-20BI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .